This invention relates generally to a semiconductor device comprising a semiconductor IC chip mounted on a carrier tape and, more particularly, to formation of such a semiconductor device without lead breakage or damage occurring during encapsulation.
Reference is made to FIGS. 6-11B for purposes of illustrating the state of the prior art of semiconductor devices of the type which comprise a semiconductor integrated circuit chip is mounted on a flexible film carrier which includes a conductive pattern comprising a plurality of thin metal leads superimposed on the surface of the film carrier. The inner leads of the pattern are connected to bonding pads on the IC chip. FIG. 6 is a plan view illustrates the condition of such a semiconductor device prior to sealing or encapsulation. FIG. 7 is a sectional view of the semiconductor device of FIG. 6 prior to encapsulation. FIG. 8 is a sectional view illustrating the condition of the semiconductor device of FIG. 6 after encapsulation. FIG. 9 is a sectional view illustrating the condition of the semiconductor device of FIG. 6 after imposition of an alternative type of encapsulation. FIG. 10 is a sectional view illustrating the condition of the semiconductor device of FIG. 6 after imposition of a still further tupe of encapsulation. FIGS. 11A and 11B are sectional views to illustrate how and where the inner leads of the semiconductor device of FIG. 6 are broken or cracked, or the inner lead ends are disengaged or partially disengaged from bonding pads due to subsequent handling and encapsulation processing.
As shown in FIGS. 6-10, film carrier 1 is formed of insulating film, which is approximately 50-125 mm thick and comprises, for example, a polymer material, such as, polyester or polyimide. Film carrier 1 is provided with series of sprocket holes 7 for its transport, and, further, contains a series of chip mounting apertures, wherein one such aperture 3, within which semiconductor IC chip 2 is mounted. The surface area of aperture 3 is made larger than surface area of chip 2. Semiconductor IC chip 2 comprises a semiconductor integrated circuit having a plurality electrode terminals or bonding pads 2A formed on the active surface of IC chip 2. A conductive pattern of leads 4, which may be comprised of copper metal foil having a width generally in the range of 50 mm to 300 mm and a thickness in the range of 15 mm to 40 mm thick, are secured to flexible film carrier 1 by means of adhesive 6. Inner leads 5 of pattern leads 4 project into aperture 3 from the aperture edge so that the lead tips or ends are free, i.e., suspended in cantilever fashion over aperture 3. The conductive pattern leads 4 are arranged in aligned relation to the configuration of bonding pads 2A of semiconductor chip 2 to extend over device aperture 3 of film carrier 1 and over the active surface of chip 2 transverse relative to the peripheral edge of chip 2.
In practice, spatial interval, B, in FIG. 7, i.e., the spacing between the edge of aperture 3 and the side surface edge of chip 2, is generally within the range of 0.15 mm to 0.40 mm. The ends of inner leads 5 are connected, e.g., by pressure melt adhesion to bonding pads 2A of semiconductor chip 2 positioned within opening 3 of film carrier 1. After the ends of inner leads 5 and electrodes 2A of semiconductor chip 2 are connected, chip 2 and a portion of conductive pattern leads 4 are sealed or encapsulated by means of sealing resin 8, as illustrated in FIG. 8. This encapsulation process may be accomplished by methods known in the art, such as, by a squeegee printing process or a resin bonding process. Then, the outer extremities of film carrier 1 and conductive pattern leads 4 are severed or trimmed to complete the construction of the semiconductor device.
In FIG. 9, semiconductor chip 2 and portions of conductive pattern leads 4 are encapsulated with sealing resin 8 after bonding pads 2A of chip 2 and the ends of inner leads 5 have been connected but with the active surface of chip 2 positioned to be facing downward or in a direction opposite to the exposure direction of the pattern of leads 4.
In FIG. 10, only the active surface of semiconductor chip 2 is encapsulated by means of sealing resin 8 after chip bonding pads 2A have been connected to the ends of inner leads 5. In this structure, the semiconductor device may be severed from film carrier 1 along a position along the spacing formed between the film aperture 3 and the outer peripheral edge of chip 2 by cutting inner leads 5 or along a position in the body of carrier 1 encircling aperture 3 thereby including a portion of inner leads 5 as secured to the carrier body.
When semiconductor chip 2 is connected to inner leads 5 with its active surface facing upward, as illustrated in FIGS. 7 and 8, inner leads 5 are suspended from film carrier 1, as seen enlarged in FIG. 11A, so that chip 2 is held in a hanging or suspended condition. Because inner leads 5 are generally made of a comparatively soft material, such as, copper having, for example, a thickness on the order of 40 mm, whereas film carrier 1 is made of harder material, such as, polyimide resin having, for example, a thickness on the order of 100 mm, a force, due to the suspension of chip 2 held by the multiple leads 4, is concentrated at points 5B of inner leads 5 along the position of aperture edge 1A. This eventually leads to the occurrence of cracks or breaks occurring at point 5B, shown at 5C in FIG. 11B, due to expansion and contraction of leads 4 over changing temperature conditions as well as tension and torsion from handling the semiconductor device during processing.
Further, when chip 2 and a portion of conductive pattern leads 4 are encapsulated with sealing resin 8, such as, shown in FIGS. 8 and 9, stress, such as, (1) heat stress during device fabrication and encapsulation and (2) mechanical stress occurring during curing and hardening of resin 8, which is in contact with inner leads 5, is concentrated at points 5B resulting in lead breaks or cracks 5C. Also, the connections of the ends of inner leads 5 to chip 2 become loosened, disengaged or partially disengaged, shown at 2B in FIG. 11B, due to the torsional effect brought upon inner leads 5 during the encapsulation and cooling of the resin sealant 8 so that poorly bonded lead/pad connections result and good electrical contact is not achieved in the end product.
Lastly, when only the active surface of semiconductor chip 2 is encapsulated with sealing resin 8 after inner leads 5 are connected to chip 2 by bonding, as illustrated in FIG. 10, external stress, resulting from the handling and transport of the semiconductor device in processing carried out after bonding and encapsulation of inner leads 5 has been accomplished, is concentrated at points 5B leading to lead breaks and fractures 5C. Further, the connections previously formed between the ends of inner leads 5 and semiconductor chip 2 become loosened or partially disengaged, which provides for poor quality bonding connections as well as poor electrical connections.
It is an object of this invention to resolve the foregoing described problems of the prior art
It is an object of this invention to provide a semiconductor device with little occurrence of inner bonding breakage and poor bonding connections resulting in a high yield production of semiconductor devices.